URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] - Rev 18

Rev	Log message	Author	Age	Path
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6446d 00h	/
17	Cosmetic changes	sybreon	6447d 04h	/
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6447d 16h	/
15	Removed ROM file. Please generate it from the SW directory.	sybreon	6454d 06h	/
14	Added initial interrupt/exception support.	sybreon	6454d 06h	/
13	Fibonacci rom	sybreon	6454d 14h	/
12	Minor changes	sybreon	6454d 14h	/
11	Removed unused signals	sybreon	6454d 14h	/
10	Fixed minor bugs	sybreon	6454d 14h	/
9	Extended testbench code	sybreon	6454d 14h	/
8	Fixed memory read-write data hazard	sybreon	6454d 14h	/
7	Added CMP instruction	sybreon	6454d 14h	/
6	Fixed C code bug which passes the test	sybreon	6454d 14h	/
5	Fixed endian correction issues on data bus.	sybreon	6455d 06h	/
4	Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.	sybreon	6463d 08h	/
3	initial import	sybreon	6480d 02h	/
2	initial import	sybreon	6480d 03h	/
1	Standard project directories initialized by cvs2svn.		6480d 03h	/