URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] - Rev 25

Rev	Log message	Author	Age	Path
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6520d 11h	/
24	Made minor performance optimisations.	sybreon	6520d 21h	/
23	Fixed minor simulation bug.	sybreon	6521d 12h	/
22	Added support for 8-bit and 16-bit data types.	sybreon	6521d 13h	/
21	Added hierarchy block diagram.	sybreon	6531d 18h	/
20	Added basic documentation doc/aeMB_datasheet.pdf	sybreon	6532d 08h	/
19	Added initial unified memory core.	sybreon	6533d 22h	/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6534d 15h	/
17	Cosmetic changes	sybreon	6535d 19h	/
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6536d 07h	/
15	Removed ROM file. Please generate it from the SW directory.	sybreon	6542d 21h	/
14	Added initial interrupt/exception support.	sybreon	6542d 21h	/
13	Fibonacci rom	sybreon	6543d 05h	/
12	Minor changes	sybreon	6543d 05h	/
11	Removed unused signals	sybreon	6543d 05h	/
10	Fixed minor bugs	sybreon	6543d 05h	/
9	Extended testbench code	sybreon	6543d 05h	/
8	Fixed memory read-write data hazard	sybreon	6543d 05h	/
7	Added CMP instruction	sybreon	6543d 05h	/
6	Fixed C code bug which passes the test	sybreon	6543d 05h	/