URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] - Rev 37

Rev	Log message	Author	Age	Path
37	This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'.		6249d 13h	/
36	Removed asynchronous reset signal.	sybreon	6249d 13h	/
35	Added async BRA/DLY signals for future clock, reset, and interrupt features.	sybreon	6250d 10h	/
34	Corrected speed issues after rev 1.9 update.	sybreon	6250d 23h	/
33	Fixed minor data hazard bug spotted by Matt Ettus.	sybreon	6266d 06h	/
32	Modified compilation sequence.	sybreon	6266d 06h	/
31	Removed byte acrobatics.	sybreon	6266d 06h	/
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6269d 07h	/
29	Added code documentation. Added new tests that test floating point, modulo arithmetic and multiplication/division.	sybreon	6269d 07h	/
28	Fixed simulation bug.	sybreon	6269d 07h	/
27	Removed some unnecessary bubble control.	sybreon	6269d 18h	/
26	Fixed minor synthesis bug.	sybreon	6269d 18h	/
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6269d 22h	/
24	Made minor performance optimisations.	sybreon	6270d 08h	/
23	Fixed minor simulation bug.	sybreon	6270d 23h	/
22	Added support for 8-bit and 16-bit data types.	sybreon	6271d 00h	/
21	Added hierarchy block diagram.	sybreon	6281d 05h	/
20	Added basic documentation doc/aeMB_datasheet.pdf	sybreon	6281d 19h	/
19	Added initial unified memory core.	sybreon	6283d 09h	/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6284d 02h	/