OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] - Rev 59

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 Added posedge/negedge bus interface.
Modified interrupt test system.
sybreon 6266d 04h /
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6267d 03h /
57 Updated documentation to EDK32 version. sybreon 6269d 04h /
56 Parameterised optional components into aeMB_xecu.v sybreon 6270d 02h /
55 Upgraded license to LGPLv3.
Significant performance optimisations.
sybreon 6270d 10h /
54 Added some compilation optimisations. sybreon 6271d 05h /
53 Added GET/PUT support through a FSL bus. sybreon 6271d 05h /
52 Added log output to iverilog.log sybreon 6271d 05h /
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6272d 08h /
50 Parameterised optional components. sybreon 6272d 12h /
49 Added random seed for simulation. sybreon 6275d 15h /
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6276d 21h /
47 Added -msoft-float and -mxl-soft-div compiler flags. sybreon 6276d 21h /
46 Minor code cleanup. sybreon 6277d 18h /
45 Minor code cleanup. sybreon 6277d 18h /
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.
sybreon 6278d 07h /
43 Added interrupt simulation.
Changed "human readable" simulation output.
sybreon 6278d 07h /
42 Enable MSR_IE with software. sybreon 6278d 08h /
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.
sybreon 6278d 23h /
40 Recommended to compile code with -O2/3/s sybreon 6289d 07h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.