URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] - Rev 60

Rev	Log message	Author	Age	Path
60	Added interrupt test routine.	sybreon	6374d 18h	/
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6374d 18h	/
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6375d 17h	/
57	Updated documentation to EDK32 version.	sybreon	6377d 18h	/
56	Parameterised optional components into aeMB_xecu.v	sybreon	6378d 16h	/
55	Upgraded license to LGPLv3. Significant performance optimisations.	sybreon	6379d 00h	/
54	Added some compilation optimisations.	sybreon	6379d 19h	/
53	Added GET/PUT support through a FSL bus.	sybreon	6379d 20h	/
52	Added log output to iverilog.log	sybreon	6379d 20h	/
51	Fixed data WISHBONE arbitration problem (reported by J Lee).	sybreon	6380d 23h	/
50	Parameterised optional components.	sybreon	6381d 02h	/
49	Added random seed for simulation.	sybreon	6384d 05h	/
48	Fixed spurious interrupt latching during long bus cycles (spotted by J Lee).	sybreon	6385d 11h	/
47	Added -msoft-float and -mxl-soft-div compiler flags.	sybreon	6385d 11h	/
46	Minor code cleanup.	sybreon	6386d 08h	/
45	Minor code cleanup.	sybreon	6386d 08h	/
44	Added better (beta) interrupt support. Changed MSR_IE to disabled at reset as per MB docs.	sybreon	6386d 21h	/
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6386d 21h	/
42	Enable MSR_IE with software.	sybreon	6386d 22h	/
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6387d 13h	/