URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] - Rev 67

Rev	Log message	Author	Age	Path
67	Minor simulation fixes.	sybreon	6085d 05h	/
66	Added fsl_tag_o to FSL bus (tag either address or data).	sybreon	6087d 03h	/
65	Fixed minor typo causing synthesis failure.	sybreon	6088d 15h	/
64	Fixed minor interrupt test typo.	sybreon	6089d 01h	/
63	Fixed interrupt signal synchronisation.	sybreon	6089d 01h	/
62	Fixed minor typo.	sybreon	6089d 01h	/
61	Changed interrupt handling system (reported by M. Ettus).	sybreon	6089d 02h	/
60	Added interrupt test routine.	sybreon	6089d 02h	/
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6089d 02h	/
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6090d 01h	/
57	Updated documentation to EDK32 version.	sybreon	6092d 02h	/
56	Parameterised optional components into aeMB_xecu.v	sybreon	6093d 00h	/
55	Upgraded license to LGPLv3. Significant performance optimisations.	sybreon	6093d 08h	/
54	Added some compilation optimisations.	sybreon	6094d 04h	/
53	Added GET/PUT support through a FSL bus.	sybreon	6094d 04h	/
52	Added log output to iverilog.log	sybreon	6094d 04h	/
51	Fixed data WISHBONE arbitration problem (reported by J Lee).	sybreon	6095d 07h	/
50	Parameterised optional components.	sybreon	6095d 10h	/
49	Added random seed for simulation.	sybreon	6098d 13h	/
48	Fixed spurious interrupt latching during long bus cycles (spotted by J Lee).	sybreon	6099d 19h	/