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Rev Log message Author Age Path
68 Generate VMEM instead of HEX dumps of programme. sybreon 6177d 03h /
67 Minor simulation fixes. sybreon 6179d 02h /
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6181d 00h /
65 Fixed minor typo causing synthesis failure. sybreon 6182d 12h /
64 Fixed minor interrupt test typo. sybreon 6182d 22h /
63 Fixed interrupt signal synchronisation. sybreon 6182d 22h /
62 Fixed minor typo. sybreon 6182d 22h /
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6182d 23h /
60 Added interrupt test routine. sybreon 6182d 23h /
59 Added posedge/negedge bus interface.
Modified interrupt test system.
sybreon 6182d 23h /
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6183d 22h /
57 Updated documentation to EDK32 version. sybreon 6185d 23h /
56 Parameterised optional components into aeMB_xecu.v sybreon 6186d 21h /
55 Upgraded license to LGPLv3.
Significant performance optimisations.
sybreon 6187d 05h /
54 Added some compilation optimisations. sybreon 6188d 01h /
53 Added GET/PUT support through a FSL bus. sybreon 6188d 01h /
52 Added log output to iverilog.log sybreon 6188d 01h /
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6189d 04h /
50 Parameterised optional components. sybreon 6189d 07h /
49 Added random seed for simulation. sybreon 6192d 11h /

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