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Rev Log message Author Age Path
34 Add cutdown non-pipelined version of core. ultra_embedded 3911d 08h /
33 Bug fixes for instruction simulator. ultra_embedded 3981d 02h /
32 Switch memory interfaces to Wishbone (pipelined).
Various bug fixes and improvements.
ultra_embedded 3981d 03h /
31 Improvements to the execute stage logic. ultra_embedded 4001d 03h /
30 Fix verilog issues which break in XST. ultra_embedded 4085d 06h /
29 Added top level makefile ultra_embedded 4085d 09h /
28 Added instruction set simulator ultra_embedded 4085d 09h /
27 Initial drop of AltOR32 v2 ultra_embedded 4086d 02h /
26 Prepare for new release ultra_embedded 4086d 03h /
25 Added Papilio Pro (XC6LX9) project.

http://papilio.gadgetfactory.net/index.php?n=Papilio.PapilioPro
ultra_embedded 4281d 04h /
24 Re-sync from local repository. ultra_embedded 4281d 05h /
23 - Bootloader code clean-up. ultra_embedded 4519d 06h /
22 - Added RTOS example project. ultra_embedded 4519d 06h /
21 - Added RTOS with port for AltOR32. ultra_embedded 4519d 07h /
20 - Added GPIO peripheral (with interrupt support). ultra_embedded 4519d 09h /
19 - IRQ_STATUS now reports all interrupts regardless of IRQ_MASK status. ultra_embedded 4519d 09h /
18 - Fixed sign extension handling of some l.sf**ui instructions. ultra_embedded 4523d 23h /
17 - Option to specify IRQ vector offset. ultra_embedded 4526d 23h /
16 - Clean-up. ultra_embedded 4526d 23h /
15 - Improved peripheral register interface.
- Papilio XC3S250E FPGA project now uses pipelined core @ 32MHz.
ultra_embedded 4527d 06h /

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