URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] - Rev 6

Rev	Log message	Author	Age	Path
6	- Simplified interrupt handling - Added optional boot address argument	ultra_embedded	4552d 10h	/
5	Added verilator simulation. Added basic peripherals & soc.	ultra_embedded	4554d 05h	/
4	Added initial basic core RTL implementation (non-pipelined).	ultra_embedded	4554d 06h	/
3	Added top level makefile. Builds simulator & executes basic test image.	ultra_embedded	4558d 11h	/
2	Added a simple simulator for OpenRisc 1000, where only the essential instructions have been implemented. Runs code compiled with the following flags: -msoft-div -msoft-float -msoft-mul -mno-ror -mno-cmov -mno-sext	ultra_embedded	4558d 12h	/
1	The project and the structure was created	root	4559d 08h	/