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Rev Log message Author Age Path
14 Re-wrote the behavioral clock generation code to more accurately
calculate the sys_clk frequency. The previous version was not
producing the correct frequency at higher frequenies due to
rounding errors.		 csantifort 5029d 00h /
13 Bug fix - added an extra state to the rx state machine to properly align
reading the uart input to the middle of each bit.		 csantifort 5029d 00h /
12 Added INITIALIZE_TO_ZERO parameter to keep instantiation
idendical to generic sram models. The parameter is not used
in the Xilinx models (they always init to zero) but it used
in the generic models.		 csantifort 5029d 00h /
11 Added vmlinux test. csantifort 5044d 00h /
10 Removed parameters for unused peruipheral modules csantifort 5045d 04h /
9 Change the format of mcr and mrc listings so they exactly match the dissasembly produced by the gnu tools.
Write ip instead of r12 in listings.		 csantifort 5045d 04h /
8 Change the value in the ID register to be compatible with the Linux code that parses it and picks a processor type. csantifort 5045d 04h /
7 Added instructions to use Veritak simulator.
Removed some unused functions from memory_configuration.v.		 csantifort 5053d 19h /
6 Set ignore property for output files csantifort 5056d 21h /
5 Deleted two temporary files that should not be in the release. csantifort 5057d 18h /
4 Corrected a couple of minor typos csantifort 5057d 18h /
3 Added trunk to $AMBER_BASE path csantifort 5057d 22h /
2 Baseline release of the Amber 2 core csantifort 5057d 22h /
1 The project and the structure was created root 5085d 01h /

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