URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] - Rev 31

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Rev	Log message	Author	Age	Path
31	Added dhrystone benchmark test	csantifort	4942d 14h	/
30	Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays	csantifort	4955d 20h	/
29	Use lgo command for saving waveforms in modelsim	csantifort	4957d 13h	/
28	Moved function prototypes to .h file	csantifort	4957d 14h	/
27	Got working with cadence nc simulator	csantifort	4990d 21h	/
26	Added wish list	csantifort	4995d 21h	/
25	Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size. Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again. Tidy up: Removed a debug message from hw/tools/run.sh	csantifort	4997d 18h	/
24	Added instructions how to build Linux kernel from source files	csantifort	4999d 18h	/
23	Split the source files list into a Vertex-6 only list and a Spartan-6 only list. That way users don;t need to delete files from the list manually if they only have a setup for one of the FPGA types.	csantifort	4999d 20h	/
22	Added files and instructions to enable the building of the vmlinux image from the kernel source files.	csantifort	5003d 19h	/
21	Fixed bug in the conditions to create the FPGA configuration log file. I added the creation of the log file in the last release, but the way it was implemented was causing the Makefile to always rebuild from the start.	csantifort	5003d 19h	/
20	Added feature to A25 core to directly use a read value from the write back stage to reduce the stall to 1 cycle when there is a register conflict with the following instruction. This increases performance by about 3%.	csantifort	5024d 19h	/
19	Create a configuration log file as part of the synthesis flow. This file is a useful reference to tell the different bitfiles apart.	csantifort	5024d 20h	/
18	Added list of source files and diagram for Amber25 core.	csantifort	5027d 18h	/
17	amber25 core bug fix. The return address for irq interrupts was off by 4 bytes when the interrupt occurred during a stm instruction with the following instruction having some register conflicts. Added test irq_stm to catch the bug. Cleaned up some header descriptions	csantifort	5028d 17h	/
16	Deleted the old version of the 3-state amber core. Its replaced with amber23. Added the 5-state Amber core.	csantifort	5031d 08h	/
15	Copied amber to amber23, Many system changes to support new amber25 core.	csantifort	5031d 08h	/
14	Re-wrote the behavioral clock generation code to more accurately calculate the sys_clk frequency. The previous version was not producing the correct frequency at higher frequenies due to rounding errors.	csantifort	5032d 20h	/
13	Bug fix - added an extra state to the rx state machine to properly align reading the uart input to the middle of each bit.	csantifort	5032d 20h	/
12	Added INITIALIZE_TO_ZERO parameter to keep instantiation idendical to generic sram models. The parameter is not used in the Xilinx models (they always init to zero) but it used in the generic models.	csantifort	5032d 20h	/

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[/] - Rev 31

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