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Rev Log message Author Age Path
37 128-bit wide boot memory module csantifort 4916d 01h /
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4916d 02h /
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 4917d 09h /
34 Tweaked strcpy function to speed it up slightly csantifort 4918d 06h /
33 Fixed bug in div assembly function. Handles negative numbers correctly.
Fixed bug in printf function, negative numbers now print correctly.
csantifort 4919d 02h /
32 Added clock cycle counting register to test_module to support dhrystone performance measurement csantifort 4920d 02h /
31 Added dhrystone benchmark test csantifort 4920d 03h /
30 Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays csantifort 4933d 09h /
29 Use lgo command for saving waveforms in modelsim csantifort 4935d 03h /
28 Moved function prototypes to .h file csantifort 4935d 03h /
27 Got working with cadence nc simulator csantifort 4968d 10h /
26 Added wish list csantifort 4973d 10h /
25 Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size.
Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again.
Tidy up: Removed a debug message from hw/tools/run.sh
csantifort 4975d 07h /
24 Added instructions how to build Linux kernel from source files csantifort 4977d 08h /
23 Split the source files list into a Vertex-6 only list and a Spartan-6 only list.
That way users don;t need to delete files from the list manually if they only have
a setup for one of the FPGA types.
csantifort 4977d 09h /
22 Added files and instructions to enable the building of the vmlinux image from the kernel source files. csantifort 4981d 08h /
21 Fixed bug in the conditions to create the FPGA configuration log file. I added the creation of the log file in the last release, but the way it was implemented was causing the Makefile to always rebuild from the start. csantifort 4981d 08h /
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.
csantifort 5002d 09h /
19 Create a configuration log file as part of the synthesis flow. This file is a useful reference to
tell the different bitfiles apart.
csantifort 5002d 09h /
18 Added list of source files and diagram for Amber25 core. csantifort 5005d 08h /

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