URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

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Rev	Log message	Author	Age	Path
38	support 128-bit wishbone now used for a25 core	csantifort	4940d 06h	/
37	128-bit wide boot memory module	csantifort	4941d 04h	/
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	4941d 05h	/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4942d 13h	/
34	Tweaked strcpy function to speed it up slightly	csantifort	4943d 09h	/
33	Fixed bug in div assembly function. Handles negative numbers correctly. Fixed bug in printf function, negative numbers now print correctly.	csantifort	4944d 06h	/
32	Added clock cycle counting register to test_module to support dhrystone performance measurement	csantifort	4945d 06h	/
31	Added dhrystone benchmark test	csantifort	4945d 06h	/
30	Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays	csantifort	4958d 13h	/
29	Use lgo command for saving waveforms in modelsim	csantifort	4960d 06h	/
28	Moved function prototypes to .h file	csantifort	4960d 07h	/
27	Got working with cadence nc simulator	csantifort	4993d 13h	/
26	Added wish list	csantifort	4998d 14h	/
25	Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size. Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again. Tidy up: Removed a debug message from hw/tools/run.sh	csantifort	5000d 11h	/
24	Added instructions how to build Linux kernel from source files	csantifort	5002d 11h	/
23	Split the source files list into a Vertex-6 only list and a Spartan-6 only list. That way users don;t need to delete files from the list manually if they only have a setup for one of the FPGA types.	csantifort	5002d 12h	/
22	Added files and instructions to enable the building of the vmlinux image from the kernel source files.	csantifort	5006d 11h	/
21	Fixed bug in the conditions to create the FPGA configuration log file. I added the creation of the log file in the last release, but the way it was implemented was causing the Makefile to always rebuild from the start.	csantifort	5006d 11h	/
20	Added feature to A25 core to directly use a read value from the write back stage to reduce the stall to 1 cycle when there is a register conflict with the following instruction. This increases performance by about 3%.	csantifort	5027d 12h	/
19	Create a configuration log file as part of the synthesis flow. This file is a useful reference to tell the different bitfiles apart.	csantifort	5027d 13h	/

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Subversion Repositories amber

[/] - Rev 38

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