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Rev Log message Author Age Path
55 Added sudo to rm mnt command csantifort 4633d 20h /
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.
csantifort 4650d 19h /
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4665d 17h /
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4665d 17h /
51 Revert vmlinux back to 48. csantifort 4706d 17h /
50 Revert to previous version csantifort 4706d 17h /
49 Added a note n how to change timeouts csantifort 4706d 17h /
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.
csantifort 4710d 23h /
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4730d 21h /
46 svn ignore vmlinux.dis and vmlinux.mem csantifort 4738d 19h /
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 4738d 19h /
44 Updated vmlinux image based on last change csantifort 4738d 19h /
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.
csantifort 4738d 19h /
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4756d 16h /
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4758d 00h /
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.
csantifort 4762d 16h /
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly
csantifort 4763d 17h /
38 support 128-bit wishbone now used for a25 core csantifort 4764d 17h /
37 128-bit wide boot memory module csantifort 4765d 15h /
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4765d 16h /

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