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Subversion Repositories amber

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Rev	Log message	Author	Age	Path
59	Added modelsim script for reloading a wlf file after a simulation has been rerun.	csantifort	4806d 10h	/
58	Use TB.clk_count for the decompiler messages and removed the local counter	csantifort	4806d 14h	/
57	Add some debug messages	csantifort	4806d 14h	/
56	Remove the timeouts file from svn. Its an output file and gets now just gets created automatically when sims are run for the first time.	csantifort	4806d 14h	/
55	Added sudo to rm mnt command	csantifort	4806d 14h	/
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4823d 14h	/
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4838d 11h	/
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4838d 11h	/
51	Revert vmlinux back to 48.	csantifort	4879d 11h	/
50	Revert to previous version	csantifort	4879d 11h	/
49	Added a note n how to change timeouts	csantifort	4879d 11h	/
48	Fixed a bug in linux that caused the os to not return to the running application after an interrupt. Hello-world now runs stand-alone again. Added initrd-200k-dhry, a disk image that uses the dhry program for init.	csantifort	4883d 18h	/
47	Changed V6 VCo from 1000Mhz to 1200 MHz	csantifort	4903d 15h	/
46	svn ignore vmlinux.dis and vmlinux.mem	csantifort	4911d 13h	/
45	Store vmlinux.mem and vmlinux.dis in compressed form	csantifort	4911d 13h	/
44	Updated vmlinux image based on last change	csantifort	4911d 14h	/
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	4911d 14h	/
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	4929d 10h	/
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	4930d 19h	/
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	4935d 11h	/

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Subversion Repositories amber

[/] - Rev 59

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