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Subversion Repositories amber

[/] - Rev 79

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Rev	Log message	Author	Age	Path
79	Added msc flash file	csantifort	4223d 20h	/
78	Added a serial debug port (using UART0) to boot-loader-ethmac	csantifort	4223d 22h	/
77	Added new a23 source files to sim and synthesis source lists.	csantifort	4225d 18h	/
76	Split the spec document into a processor core spec, and a user guide.	csantifort	4225d 18h	/
75	Fixed scripts after renaming boot-loader to boot-loader-serial	csantifort	4231d 16h	/
74	The patch implements barrel shifter using rotate as a main primitive. The design was optimized for Altera Cyclone III FPGA and can be reused with other FPGA vendors and products. The patch integrates the FPGA-optimized barrel shifter into the Amber 23 core when it is build for Altera FPGA. The patch reduces footprint from 1178 to 339 LEs keeping Fmax at 57-60 MHz. Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4231d 17h	/
73	The patch introduces a new configuration option `A23_RAM_REGISTER_BANK, which controls instantiation of Amber 23 register bank. If the option is set, a ram-based variant of the register bank is instantiated. It can be useful in low-end FPGA designs, where flipflops and muxes are costly. Altera Cyclone III resource utilization: - flipflop-based register bank: 1583 combinationals + 856 registers - ram-based register bank: 268 combinationals + 156 registers Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4231d 17h	/
72	5 bit "OH_USR" constant was used when 2 bit "USR" should be used. Both of the constants are 0. The fault was introduced by ram-based register bank commit. Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4231d 17h	/
71	Original Amber 23 core uses asyncronous implementation of register bank. It leads to some problems with ram-based implementation of the register bank, because at least Altera FPGAs uses syncronous ram blocks, so the whole address needs to be latched. The patch exposes non-registered versions of register select signals to the register bank, so the bank can build address and latch it in the syncronous ram input register. The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA. Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4231d 17h	/
70	The mlas_bug testcase tried to use stack without setting stack pointer register, causing unpredictable behavoiur. The patch uses an expilict stack area for the test. Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4231d 17h	/
69	Updated the spec for ISE 14.5, boot-loader-ethmac.	csantifort	4231d 17h	/
68	Remove modelsim files. Only supporting Xilinx isim now.	csantifort	4231d 18h	/
67	renamed boot-loader.c to boot-loader-serial.c	csantifort	4231d 18h	/
66	Remove the stand-alone ethmac test. Use boot-loader-ethmac instead to verify ethmac functionality.	csantifort	4231d 18h	/
65	Renamed boot-loader to boot-loader-serial	csantifort	4231d 18h	/
64	Support latest Xilinx ISE 14.5 software.	csantifort	4231d 19h	/
63	Add support for Xilinx ISim Verilog simulator. Remove Virtex-6 files.	csantifort	4231d 23h	/
62	Added source for amber-pkt2mem	csantifort	4384d 12h	/
61	Add new netowkr based boot loader. Remove support for Virtex. Spartan 6 only now.	csantifort	4518d 17h	/
60	Bug fix; removed a combinational loop from the a25_decode logic.	csantifort	4736d 14h	/

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[/] - Rev 79

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