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Subversion Repositories apbi2c

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Rev Log message Author Age Path
25 removing unnecessary file. redbear 3871d 23h /
24 Correcetd modules and back again toold plan on fifo using only registers. redbear 3872d 00h /
23 correcting TX FSM redbear 3886d 05h /
22 Correcting TX transmission and remove tri state from RTL. redbear 3887d 00h /
21 added tri state on module i2c redbear 3900d 03h /
20 Finished a previous version from RX and added SDA and SCL enable to PADS. redbear 3900d 22h /
19 changes about area use for proprely use. redbear 3945d 22h /
18 Corrected fifo mem acess, i2c_module and revised conections on top redbear 3962d 22h /
17 fifo.v and dual_port_ram.v celaya.dario 3963d 22h /
16 fifo.v and dual_port_ram.v celaya.dario 3963d 22h /
15 11'd1 to 4'd1 redbear 3970d 05h /
14 added a and to make real full fifo. redbear 3970d 05h /
13 re write all fifo module to write and give full when the same is not full redbear 3970d 05h /
12 added PSELx on WR_ENA, RD_ENA to correct read/write when PSEL is HIGH redbear 3970d 05h /
11 Added configuration to define RX and TX operation and configure propely the ports. redbear 3977d 01h /
10 Correcting a few words wrote wrong. redbear 3977d 01h /
9 More description added on spec redbear 3978d 03h /
8 More description added on spec redbear 3978d 03h /
7 Corrected CLOCK generated by SCL according NXP spec. redbear 3979d 03h /
6 Adding a basic FSM to RX. redbear 3984d 04h /

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