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Rev Log message Author Age Path
22 Correcting TX transmission and remove tri state from RTL. redbear 3691d 15h /
21 added tri state on module i2c redbear 3704d 18h /
20 Finished a previous version from RX and added SDA and SCL enable to PADS. redbear 3705d 13h /
19 changes about area use for proprely use. redbear 3750d 13h /
18 Corrected fifo mem acess, i2c_module and revised conections on top redbear 3767d 13h /
17 fifo.v and dual_port_ram.v celaya.dario 3768d 14h /
16 fifo.v and dual_port_ram.v celaya.dario 3768d 14h /
15 11'd1 to 4'd1 redbear 3774d 20h /
14 added a and to make real full fifo. redbear 3774d 20h /
13 re write all fifo module to write and give full when the same is not full redbear 3774d 20h /
12 added PSELx on WR_ENA, RD_ENA to correct read/write when PSEL is HIGH redbear 3774d 20h /
11 Added configuration to define RX and TX operation and configure propely the ports. redbear 3781d 16h /
10 Correcting a few words wrote wrong. redbear 3781d 16h /
9 More description added on spec redbear 3782d 18h /
8 More description added on spec redbear 3782d 18h /
7 Corrected CLOCK generated by SCL according NXP spec. redbear 3783d 18h /
6 Adding a basic FSM to RX. redbear 3788d 19h /
5 Added about APB address necessary to read and write on FIFOS and register configuration. redbear 3796d 16h /
4 Added on module I2C basic error for register configuration redbear 3796d 19h /
3 Added a basic example on I2C Block. redbear 3796d 19h /

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