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Rev Log message Author Age Path
82 correct some typoes, thanks to Hu, Tao wsong0210 4051d 16h /
81 adding a solution in README to a cell lib problem. wsong0210 4419d 15h /
80 make the README file more understandable wsong0210 4499d 12h /
79 update comments in sim compile.sh to clarify that synthesis must be done before post-synthesis simulation wsong0210 4559d 22h /
78 pass link wsong0210 4726d 09h /
77 pass syn elaboration wsong0210 4727d 09h /
76 fix syntex wsong0210 4731d 09h /
75 code finished, start the debugging wsong0210 4731d 09h /
74 in/out buffer finished wsong0210 4732d 09h /
73 input buffer wsong0210 4739d 08h /
72 clos-opt ongoing, Clos switch finished, nxt input buffer wsong0210 4740d 09h /
71 the buffered 2-stage Clos switch wsong0210 4741d 09h /
70 clos-opt ongoing wsong0210 4741d 09h /
69 central module of the Clos wsong0210 4744d 09h /
68 rewite the clos switch in the SDM-Clos-buf router wsong0210 4745d 09h /
67 structure not good, prepare to use new files wsong0210 4745d 10h /
66 clos opt ongoing wsong0210 4760d 03h /
65 pipeline controller wsong0210 4760d 04h /
64 clos opt ongoing wsong0210 4760d 04h /
63 clos opt ongoing wsong0210 4760d 08h /

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