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Rev Log message Author Age Path
46 VC test bench ready wsong0210 4765d 11h /
45 vc test bench in debugging wsong0210 4767d 08h /
44 the testbench for VC routers before debugging wsong0210 4768d 09h /
43 rtdriver for VC router wsong0210 4769d 08h /
42 VC synthesis script ready wsong0210 4771d 09h /
41 vc synthesis scripts, initial version wsong0210 4771d 10h /
40 VC router HDL all cleaned up wsong0210 4771d 10h /
39 clean up the VC router wsong0210 4771d 10h /
38 clean up the VC router wsong0210 4772d 03h /
37 SDM/wormhole ready wsong0210 4772d 08h /
36 add simply description wsong0210 4772d 09h /
35 test bench ready wsong0210 4772d 10h /
34 debug wsong0210 4773d 10h /
33 debug wsong0210 4773d 11h /
32 currently debugging the simulation compiling wsong0210 4774d 08h /
31 test bench ongoing wsong0210 4775d 08h /
30 test bench cleaning up ongping wsong0210 4776d 08h /
29 begin the test environment wsong0210 4777d 08h /
28 merge the synthesis scripts in the branch init to trunk wsong0210 4777d 09h /
27 eliminate timing loops in all router architectures wsong0210 4777d 09h /

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