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Rev	Log message	Author	Age	Path
35	Added old uploaded documents to new repository.	root	5718d 01h	/
34	Added old uploaded documents to new repository.	root	5718d 19h	/
33	New directory structure.	root	5718d 19h	/
32	Fixed a potential bug where the core was forced into an unknown state when an asynchronous reset was given without a running clock.	rherveille	8205d 08h	/
31	Changed internal counter libraries. Split counter.vhd into separate files. Core is in same state as Verilog version now.	rherveille	8284d 10h	/
30	Fixed data-latch bug (posedge ata_diow instead of negedge ata_diow).	rherveille	8288d 08h	/
29	no message	rherveille	8294d 23h	/
28	renamed IO names revised document	rherveille	8294d 23h	/
27	renamed all files to 'atahost_***.vhd' broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' changed resD input to generic RESD in ud_cnt.vhd changed ID input to generic ID in ro_cnt.vhd changed core to reflect changes in ro_cnt.vhd removed references to 'count' library changed IO names added disclaimer added CVS log moved registers and wishbone signals into 'atahost_wb_slave.vhd'	rherveille	8294d 23h	/
26	renamed 'atahost.vhd' to 'atahost_top.vhd' renamed 'controller.vhd' to 'atahost_controller.vhd' renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd' broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' changed resD input to generic RESD in ud_cnt.vhd changed ID input to generic ID in ro_cnt.vhd changed core to reflect changes in ro_cnt.vhd removed references to 'count' library changed IO names added disclaimer added CVS log moved registers and wishbone signals into 'atahost_wb_slave.vhd'	rherveille	8294d 23h	/
25	renamed 'atahost.vhd' to 'atahost_top.vhd' renamed 'controller.vhd' to 'atahost_controller.vhd' renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd' broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' changed resD input to generic RESD in ud_cnt.vhd changed ID input to generic ID in ro_cnt.vhd changed core to reflect changes in ro_cnt.vhd removed references to 'count' library changed IO names added disclaimer added CVS log moved registers and wishbone signals into 'atahost_wb_slave.vhd' core is now equivalent to verilog version	rherveille	8294d 23h	/
24	Initial Verilog HDL release	rherveille	8294d 23h	/
23	Moved wishbone interface into 'atahost_wb_slave.v' Major revisions in all cores.	rherveille	8294d 23h	/
22	Added disclaimer Added CVS information Changed core for new internal counter libraries (synthesis fixes).	rherveille	8297d 03h	/
21	Changed atahost_top pin-information.	rherveille	8297d 03h	/
20	Some minor bug fixes	rherveille	8410d 23h	/
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8420d 05h	/
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8448d 08h	/
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8454d 05h	/
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8481d 04h	/

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[/] - Rev 35

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