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Rev Log message Author Age Path
7 New VHDL translation added. This new file has been verified in actual hardware. It is stable. jclaytons 4270d 23h /
6 Added old uploaded documents to new repository. root 5732d 12h /
5 Added old uploaded documents to new repository. root 5733d 05h /
4 New directory structure. root 5733d 05h /
3 This commit was manufactured by cvs2svn to create tag 'V001'. 6964d 18h /
2 Finally adding some files to CVS tree. jclaytons 6964d 18h /
1 Standard project directories initialized by cvs2svn. 6964d 18h /

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