URL https://opencores.org/ocsvn/ax4lbr/ax4lbr/trunk

Subversion Repositories ax4lbr

[/] - Rev 10

Rev	Log message	Author	Age	Path
10	Corrected a few errors in axil2wb.vhd. Marek Guminski detected a problem with xREADY asserted when ARESETN is low. The synchronizer has been improved (asynchronous reset!) Added generics controlling if the reset should be synchronized and if the errors should be masked (as bus error crash ARM in MPSoCs).	wzab	178d 01h	/
9	Corrected two serious errors from the previous release.	wzab	178d 06h	/
8	Fixed problem in axil2wb.vhd, which could result in a very rare problems. If the master issued read and write commands in the same cycle (acceptable in AXI4LITE), the read transaction was lost, resulting in bus error and crashing ARM. Please note that axil2ipb is not fixed yet.	wzab	178d 07h	/
7	The previous versions could not issue BVALID=1 or RVALID=1 if BREADY or RREADY was already high. That could result in freezing the bus. This version eliminates that problem.	wzab	184d 08h	/
6	Completely reworked axil2ipb.vhd for compatibility with Versal CIPS	wzab	225d 02h	/
5	Completely reworked axil2wb.vhd for compatibility with Versal CIPS	wzab	225d 23h	/
4	Added AWPROT and ARPROT ports required by Altera Qsys (commented out)	wzab	3753d 11h	/
3	Small correction of description	wzab	3753d 12h	/
2	Initial commit of files from https://github.com/wzab/vextproj (directory version_2).	wzab	3753d 12h	/
1	The project and the structure was created	root	3753d 12h	/