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14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 4064d 13h /
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 4064d 18h /
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 4073d 22h /
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 4075d 16h /
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 4079d 16h /
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 4082d 12h /
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4182d 18h /
7 [minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors). daniel.kho 4186d 12h /
6 [minor]: expanded some waveforms and show random stimulus from simulation script. daniel.kho 4186d 17h /
5 [minor]: refactored type names to use the convention 't_*' for more clarity. AXI4-Stream signal names also starts with a 't'. daniel.kho 4186d 21h /
4 [minor]: Removed unused libraries from simulation script. daniel.kho 4187d 15h /
3 Updated user.vhdl to use math_real's uniform for testbench randomisation. This is to avoid having to include third-party libraries into the project. Simulation of user.vhdl works - writeStream() procedure is used to send AXI4-Stream bus writes. More verification will follow. daniel.kho 4187d 16h /
2 Initial commit.
Added packages and usage example for AXI4-Stream protocol.
Added simulation scripts for ModelSim/QuestaSim.		 daniel.kho 4188d 02h /
1 The project and the structure was created root 4188d 13h /

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