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Subversion Repositories axi4_tlm_bfm

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16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 4155d 00h /
15 [minor]: cleaned up sources. daniel.kho 4157d 07h /
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 4165d 21h /
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 4166d 02h /
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 4175d 06h /
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 4177d 00h /
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 4181d 01h /
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 4183d 21h /
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4284d 02h /
7 [minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors). daniel.kho 4287d 21h /
6 [minor]: expanded some waveforms and show random stimulus from simulation script. daniel.kho 4288d 01h /
5 [minor]: refactored type names to use the convention 't_*' for more clarity. AXI4-Stream signal names also starts with a 't'. daniel.kho 4288d 05h /
4 [minor]: Removed unused libraries from simulation script. daniel.kho 4288d 23h /
3 Updated user.vhdl to use math_real's uniform for testbench randomisation. This is to avoid having to include third-party libraries into the project. Simulation of user.vhdl works - writeStream() procedure is used to send AXI4-Stream bus writes. More verification will follow. daniel.kho 4289d 00h /
2 Initial commit.
Added packages and usage example for AXI4-Stream protocol.
Added simulation scripts for ModelSim/QuestaSim.		 daniel.kho 4289d 10h /
1 The project and the structure was created root 4289d 21h /

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