OpenCores
URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] - Rev 27

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
27 Updated simulation scripts. daniel.kho 3907d 04h /
26 Refactored simulation folders. daniel.kho 3907d 05h /
25 Refactored folders. daniel.kho 3907d 05h /
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3907d 05h /
23 Added top-level user example used in technical paper. daniel.kho 3914d 23h /
22 Added pin assignments for BeMicro kit. Added demo top-level used in technical paper. daniel.kho 3914d 23h /
21 Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. daniel.kho 3918d 01h /
20 Updated simulation scripts. daniel.kho 3918d 01h /
19 Updated synthesis constraints and scripts. daniel.kho 3918d 01h /
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3918d 01h /
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3918d 02h /
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 4020d 22h /
15 [minor]: cleaned up sources. daniel.kho 4023d 05h /
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 4031d 19h /
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 4031d 23h /
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 4041d 04h /
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 4042d 22h /
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 4046d 22h /
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 4049d 18h /
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4150d 00h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.