URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

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Rev	Log message	Author	Age	Path
32	Added compile+simulate script for Windows.	daniel.kho	3930d 06h	/
31	Added initial Xilinx Vivado synthesis scripts and constraints.	daniel.kho	3944d 04h	/
30	Refactored synthesis scripts.	daniel.kho	3944d 04h	/
29	Updated simulation scripts.	daniel.kho	3944d 04h	/
28	Temporarily remove simulation folder.	daniel.kho	3944d 04h	/
27	Updated simulation scripts.	daniel.kho	3944d 04h	/
26	Refactored simulation folders.	daniel.kho	3944d 05h	/
25	Refactored folders.	daniel.kho	3944d 05h	/
24	Updated simulation sources to reflect changes made for synthesis.	daniel.kho	3944d 05h	/
23	Added top-level user example used in technical paper.	daniel.kho	3951d 23h	/
22	Added pin assignments for BeMicro kit. Added demo top-level used in technical paper.	daniel.kho	3951d 23h	/
21	Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version.	daniel.kho	3955d 01h	/
20	Updated simulation scripts.	daniel.kho	3955d 02h	/
19	Updated synthesis constraints and scripts.	daniel.kho	3955d 02h	/
18	Added hardware PRBS generator, modularised top-level by having separate file as the tester.	daniel.kho	3955d 02h	/
17	Added more pipelining, enhancements. Tested on BeMicro kit.	daniel.kho	3955d 02h	/
16	Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input.	daniel.kho	4057d 22h	/
15	[minor]: cleaned up sources.	daniel.kho	4060d 05h	/
14	Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap.	daniel.kho	4068d 19h	/
13	Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well.	daniel.kho	4069d 00h	/

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Subversion Repositories axi4_tlm_bfm

[/] - Rev 32

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