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Rev Log message Author Age Path
16 RobustVerilog version 1.4 compatible eyalhoc 4752d 13h /
15 Support RobustVerilog project eyalhoc 4764d 23h /
14 GUI support eyalhoc 4771d 18h /
13 eyalhoc 4780d 18h /
12 create prgen rand eyalhoc 4797d 19h /
11 support single slave eyalhoc 4798d 00h /
10 minor fixes eyalhoc 4800d 02h /
9 add insert_rand task eyalhoc 4803d 02h /
8 use match signals eyalhoc 4803d 02h /
7 allow no user bits eyalhoc 4803d 02h /
6 added check_single and write_and_check_single tasks
added option to random data by address
eyalhoc 4812d 17h /
5 added dos batch file for windows eyalhoc 4815d 19h /
4 eyalhoc 4821d 15h /
3 eyalhoc 4821d 19h /
2 eyalhoc 4821d 19h /
1 The project and the structure was created root 4823d 17h /

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