OpenCores

URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] - Rev 19

Go to most recent revision

Filtering Options

Rev	Log message	Author	Age	Path
19	Minor changes.	ash_riple	4235d 08h	/
18	Added support for Xilinx Chips. Added support for AXI4-Lite bus. Can be used as an XPS IP.	ash_riple	4235d 09h	/
17	Added unreachable trigger condition "@WR & @RD" checking.	ash_riple	4481d 12h	/
16	Released version 2.2.	ash_riple	4503d 12h	/
15	Released version 2.2.	ash_riple	4503d 12h	/
14	Changed dec to hex value of triggerPnum.	ash_riple	4504d 03h	/
13	Added minor syntax changes and Linux environment simulation script.	ash_riple	4504d 08h	/
12	Added timing information to the capture content.	ash_riple	4504d 16h	/
11	Added pre-trigger capture.	ash_riple	4505d 08h	/
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4510d 13h	/
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4511d 08h	/
8	Added fault handling of wrong input length in the GUI.	ash_riple	4515d 07h	/
7	Added references related to "Bus Monitor".	ash_riple	4515d 12h	/
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4516d 08h	/
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4519d 08h	/
4	Created tag for original source code. Version 1.0.	ash_riple	4519d 11h	/
3	Added original article.	ash_riple	4519d 11h	/
2	Checked in working code base.	ash_riple	4523d 07h	/
1	The project and the structure was created	root	4523d 22h	/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.