URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] - Rev 19

Rev	Log message	Author	Age	Path
19	FPGA Pin desription added.	jsauermann	7300d 02h	/
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7601d 01h	/
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7601d 01h	/
16	Enable interrupts at start of each task. This fix is required after a change in opcode_decoder.vhd.	jsauermann	7601d 01h	/
15	sample ucf file	jsauermann	7640d 04h	/
14	no message	jsauermann	7648d 05h	/
13	bug in print_unsigned() fixed. Now done as in rtos.c	jsauermann	7690d 23h	/
12	Todo removed	jsauermann	7719d 21h	/
11	First Version	jsauermann	7719d 21h	/
10	Set top of stack of idle task to end of internal memory rather than end of external memory (causing incorrect display of 100 % CPU load).	jsauermann	7719d 22h	/
9	Made cpu_engine WISHBONE compliant. (Somebody please validate it).	jsauermann	7719d 23h	/
8	Initialization of compound auto variables added (was TODO)	jsauermann	7727d 01h	/
7	Handle auto variable declarations in compound statements properly	jsauermann	7728d 01h	/
6	New Target polled for testing compiler without the need to simulate interrupts	jsauermann	7728d 01h	/
5	Initial version	jsauermann	7728d 22h	/
4	Documentation finalized	jsauermann	7729d 02h	/
3	This commit was manufactured by cvs2svn to create tag 'V10'.		7731d 21h	/
2	no message	jsauermann	7731d 21h	/
1	Standard project directories initialized by cvs2svn.		7731d 21h	/