URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] - Rev 33

Rev	Log message	Author	Age	Path
33	changed to newer gcc/bison versions	jsauermann	4493d 04h	/
32	changed to newer gcc/bison versions	jsauermann	4493d 05h	/
31	changed to newer gcc/bison versions	jsauermann	4493d 05h	/
30	changed to newer gcc/bison versions	jsauermann	4493d 05h	/
29	fixed problems reported by buaa.byl	jsauermann	4493d 06h	/
28	Added old uploaded documents to new repository.	root	5737d 10h	/
27	Added old uploaded documents to new repository.	root	5738d 03h	/
26	New directory structure.	root	5738d 03h	/
25	XOR bug fixed	jsauermann	6796d 09h	/
24	no message	jsauermann	6957d 08h	/
23	Fixed problem with wishbone wait-states	jsauermann	7097d 07h	/
22	This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_7'.		7097d 12h	/
21	Changes for Xilinx Proj. Nav. 7.1.02i	jsauermann	7097d 12h	/
20	This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_5'.		7293d 09h	/
19	FPGA Pin desription added.	jsauermann	7293d 09h	/
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7594d 08h	/
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7594d 08h	/
16	Enable interrupts at start of each task. This fix is required after a change in opcode_decoder.vhd.	jsauermann	7594d 08h	/
15	sample ucf file	jsauermann	7633d 11h	/
14	no message	jsauermann	7641d 12h	/