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112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7647d 00h /
111 Fixed according to the linter.
Case statement for data_out joined.
mohor 7649d 00h /
110 Fixed according to the linter. mohor 7649d 00h /
109 Fixed according to the linter. mohor 7649d 01h /
108 Fixed according to the linter. mohor 7649d 02h /
107 Fixed according to the linter. mohor 7649d 02h /
106 Unused signal removed. mohor 7655d 00h /
105 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7655d 13h /
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.
tadejm 7655d 13h /
103 This commit was manufactured by cvs2svn to create tag 'complete_1'. 7658d 04h /
102 Little fixes (to fix warnings). mohor 7658d 04h /
101 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7662d 06h /
100 Synchronization changed. mohor 7662d 06h /
99 PCI_BIST replaced with CAN_BIST. mohor 7662d 06h /
98 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7667d 17h /
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7667d 17h /
96 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7667d 18h /
95 Virtual silicon ram instances added. simons 7667d 18h /
94 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7673d 05h /
93 synthesis full_case parallel_case fixed. mohor 7673d 05h /

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