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[/] - Rev 118

Rev	Log message	Author	Age	Path
118	Artisan RAM fixed (when not using BIST).	mohor	7756d 03h	/
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7756d 03h	/
116	This commit was manufactured by cvs2svn to create tag 'rel_14'.		7761d 21h	/
115	Artisan ram instances added.	simons	7761d 21h	/
114	This commit was manufactured by cvs2svn to create tag 'rel_13'.		7788d 22h	/
113	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7788d 22h	/
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7788d 22h	/
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7790d 22h	/
110	Fixed according to the linter.	mohor	7790d 22h	/
109	Fixed according to the linter.	mohor	7790d 23h	/
108	Fixed according to the linter.	mohor	7791d 00h	/
107	Fixed according to the linter.	mohor	7791d 00h	/
106	Unused signal removed.	mohor	7796d 22h	/
105	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7797d 11h	/
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7797d 11h	/
103	This commit was manufactured by cvs2svn to create tag 'complete_1'.		7800d 02h	/
102	Little fixes (to fix warnings).	mohor	7800d 02h	/
101	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7804d 04h	/
100	Synchronization changed.	mohor	7804d 04h	/
99	PCI_BIST replaced with CAN_BIST.	mohor	7804d 04h	/