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[/] - Rev 122

Rev	Log message	Author	Age	Path
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7737d 09h	/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7737d 09h	/
120	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7746d 06h	/
119	Artisan RAMs added.	mohor	7746d 06h	/
118	Artisan RAM fixed (when not using BIST).	mohor	7746d 06h	/
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7746d 06h	/
116	This commit was manufactured by cvs2svn to create tag 'rel_14'.		7752d 00h	/
115	Artisan ram instances added.	simons	7752d 00h	/
114	This commit was manufactured by cvs2svn to create tag 'rel_13'.		7779d 01h	/
113	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7779d 01h	/
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7779d 01h	/
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7781d 01h	/
110	Fixed according to the linter.	mohor	7781d 01h	/
109	Fixed according to the linter.	mohor	7781d 02h	/
108	Fixed according to the linter.	mohor	7781d 03h	/
107	Fixed according to the linter.	mohor	7781d 03h	/
106	Unused signal removed.	mohor	7787d 01h	/
105	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7787d 14h	/
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7787d 14h	/
103	This commit was manufactured by cvs2svn to create tag 'complete_1'.		7790d 05h	/