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134 Active high/low problem when Altera devices are used. Bug fixed by
Rojhalat Ibrahim.
mohor 7679d 06h /
133 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7685d 17h /
132 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7685d 17h /
131 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7685d 17h /
130 mbist signals updated according to newest convention markom 7685d 17h /
129 Error counters changed. mohor 7702d 02h /
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7702d 02h /
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7702d 02h /
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.
mohor 7702d 22h /
125 Synchronization changed, error counters fixed. mohor 7707d 04h /
124 ALTERA_RAM supported. mohor 7727d 10h /
123 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7734d 16h /
122 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7734d 16h /
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.
mohor 7734d 16h /
120 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7743d 13h /
119 Artisan RAMs added. mohor 7743d 13h /
118 Artisan RAM fixed (when not using BIST). mohor 7743d 13h /
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.
mohor 7743d 13h /
116 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7749d 07h /
115 Artisan ram instances added. simons 7749d 07h /

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