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Rev Log message Author Age Path
48 Actel APA ram supported. mohor 7787d 16h /
47 Data is latched on read. mohor 7787d 16h /
46 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7797d 14h /
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.
mohor 7797d 14h /
44 When bit error occured while active error flag was transmitted, counter was
not incremented.
mohor 7797d 15h /
43 Directory keeper. mohor 7797d 22h /
42 Initial version of the project. mohor 7797d 22h /
41 Incomplete sensitivity list fixed. mohor 7797d 23h /
40 Typo fixed. mohor 7798d 00h /
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.
mohor 7798d 00h /
38 Temporary backup version (still fully operable). mohor 7799d 14h /
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7799d 14h /
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.
mohor 7799d 14h /
35 Several registers added. Not finished, yet. mohor 7802d 18h /
34 Errors monitoring improved. arbitration_lost improved. mohor 7805d 00h /
33 abort_tx added. mohor 7805d 00h /
32 abort_tx added. Bit destuff fixed. mohor 7805d 00h /
31 Wishbone interface added. mohor 7806d 14h /
30 CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added.
mohor 7806d 23h /
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.
mohor 7807d 20h /

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