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Rev Log message Author Age Path
48 Actel APA ram supported. mohor 8003d 23h /
47 Data is latched on read. mohor 8004d 00h /
46 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8013d 22h /
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.
mohor 8013d 22h /
44 When bit error occured while active error flag was transmitted, counter was
not incremented.
mohor 8013d 23h /
43 Directory keeper. mohor 8014d 05h /
42 Initial version of the project. mohor 8014d 05h /
41 Incomplete sensitivity list fixed. mohor 8014d 07h /
40 Typo fixed. mohor 8014d 07h /
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.
mohor 8014d 08h /
38 Temporary backup version (still fully operable). mohor 8015d 22h /
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 8015d 22h /
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.
mohor 8015d 22h /
35 Several registers added. Not finished, yet. mohor 8019d 02h /
34 Errors monitoring improved. arbitration_lost improved. mohor 8021d 08h /
33 abort_tx added. mohor 8021d 08h /
32 abort_tx added. Bit destuff fixed. mohor 8021d 08h /
31 Wishbone interface added. mohor 8022d 21h /
30 CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added.
mohor 8023d 06h /
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.
mohor 8024d 04h /

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