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[/] - Rev 49

Rev	Log message	Author	Age	Path
49	Actel APA ram changed. Now synchronous read is used.	mohor	7819d 01h	/
48	Actel APA ram supported.	mohor	7819d 02h	/
47	Data is latched on read.	mohor	7819d 02h	/
46	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7829d 00h	/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7829d 00h	/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7829d 01h	/
43	Directory keeper.	mohor	7829d 08h	/
42	Initial version of the project.	mohor	7829d 08h	/
41	Incomplete sensitivity list fixed.	mohor	7829d 10h	/
40	Typo fixed.	mohor	7829d 10h	/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7829d 10h	/
38	Temporary backup version (still fully operable).	mohor	7831d 00h	/
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7831d 00h	/
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7831d 01h	/
35	Several registers added. Not finished, yet.	mohor	7834d 04h	/
34	Errors monitoring improved. arbitration_lost improved.	mohor	7836d 10h	/
33	abort_tx added.	mohor	7836d 10h	/
32	abort_tx added. Bit destuff fixed.	mohor	7836d 10h	/
31	Wishbone interface added.	mohor	7838d 00h	/
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7838d 09h	/