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Rev Log message Author Age Path
50 Top level signal names changed. mohor 7882d 02h /
49 Actel APA ram changed. Now synchronous read is used. mohor 7885d 18h /
48 Actel APA ram supported. mohor 7885d 18h /
47 Data is latched on read. mohor 7885d 18h /
46 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7895d 17h /
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.
mohor 7895d 17h /
44 When bit error occured while active error flag was transmitted, counter was
not incremented.
mohor 7895d 18h /
43 Directory keeper. mohor 7896d 00h /
42 Initial version of the project. mohor 7896d 00h /
41 Incomplete sensitivity list fixed. mohor 7896d 02h /
40 Typo fixed. mohor 7896d 02h /
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.
mohor 7896d 02h /
38 Temporary backup version (still fully operable). mohor 7897d 17h /
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7897d 17h /
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.
mohor 7897d 17h /
35 Several registers added. Not finished, yet. mohor 7900d 21h /
34 Errors monitoring improved. arbitration_lost improved. mohor 7903d 03h /
33 abort_tx added. mohor 7903d 03h /
32 abort_tx added. Bit destuff fixed. mohor 7903d 03h /
31 Wishbone interface added. mohor 7904d 16h /

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