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Rev Log message Author Age Path
56 Doubled declarations removed. mohor 7783d 13h /
55 wire declaration added. mohor 7783d 13h /
54 This commit was manufactured by cvs2svn to create tag 'branch-release-1-0'. 7788d 15h /
53 CAN pins located. mohor 7788d 15h /
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7788d 15h /
51 Xilinx RAM added. mohor 7788d 16h /
50 Top level signal names changed. mohor 7788d 16h /
49 Actel APA ram changed. Now synchronous read is used. mohor 7792d 08h /
48 Actel APA ram supported. mohor 7792d 08h /
47 Data is latched on read. mohor 7792d 08h /
46 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7802d 06h /
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.
mohor 7802d 06h /
44 When bit error occured while active error flag was transmitted, counter was
not incremented.
mohor 7802d 08h /
43 Directory keeper. mohor 7802d 14h /
42 Initial version of the project. mohor 7802d 14h /
41 Incomplete sensitivity list fixed. mohor 7802d 16h /
40 Typo fixed. mohor 7802d 16h /
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.
mohor 7802d 16h /
38 Temporary backup version (still fully operable). mohor 7804d 07h /
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7804d 07h /

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