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[/] - Rev 64

Rev	Log message	Author	Age	Path
64	* empty log message *	mohor	7772d 19h	/
63	ALE changes on negedge of clk.	mohor	7778d 16h	/
62	can_cs signal used for generation of the cs.	mohor	7778d 16h	/
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7781d 06h	/
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7781d 07h	/
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7781d 08h	/
58	timescale.v is used for simulation only.	mohor	7781d 19h	/
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7781d 19h	/
56	Doubled declarations removed.	mohor	7782d 18h	/
55	wire declaration added.	mohor	7782d 19h	/
54	This commit was manufactured by cvs2svn to create tag 'branch-release-1-0'.		7787d 20h	/
53	CAN pins located.	mohor	7787d 20h	/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7787d 20h	/
51	Xilinx RAM added.	mohor	7787d 21h	/
50	Top level signal names changed.	mohor	7787d 21h	/
49	Actel APA ram changed. Now synchronous read is used.	mohor	7791d 13h	/
48	Actel APA ram supported.	mohor	7791d 13h	/
47	Data is latched on read.	mohor	7791d 13h	/
46	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7801d 12h	/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7801d 12h	/