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Rev	Log message	Author	Age	Path
90	paralel_case and full_case compiler directives added to case statements.	mohor	7660d 02h	/
89	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7660d 23h	/
88	Previous change removed. When resynchronization occurs we go to seg1 stage. sync stage does not cause another start of seg1 stage.	mohor	7660d 23h	/
87	When hard_sync or resync occure we need to go to seg1 segment. Going to sync segment is in that case blocked.	mohor	7661d 00h	/
86	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7662d 15h	/
85	Typo fixed.	mohor	7662d 15h	/
84	clk_cnt reduced from [8:0] to [6:0].	mohor	7663d 22h	/
83	cs_can_i is used only when WISHBONE interface is not used.	mohor	7663d 23h	/
82	Removed few signals.	mohor	7664d 00h	/
81	"chip select" signal cs_can_i is used only when not using WISHBONE interface.	mohor	7664d 00h	/
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7664d 00h	/
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7665d 00h	/
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7665d 00h	/
77	Synchronization is also needed when transmitting a message.	mohor	7667d 23h	/
76	Counters width changed.	mohor	7667d 23h	/
75	When switching to tx, sync stage is overjumped.	mohor	7670d 00h	/
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7670d 05h	/
73	overrun and length_info fifos are initialized at the end of reset.	mohor	7670d 05h	/
72	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7672d 03h	/
71	Ports added for the CAN_BIST.	mohor	7672d 03h	/

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