OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] - Rev 95

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
95 Virtual silicon ram instances added. simons 7653d 10h /
94 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7658d 21h /
93 synthesis full_case parallel_case fixed. mohor 7658d 21h /
92 clkout is clk/2 after the reset. mohor 7659d 06h /
91 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7659d 19h /
90 paralel_case and full_case compiler directives added to case statements. mohor 7659d 19h /
89 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7660d 16h /
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.
mohor 7660d 16h /
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.
mohor 7660d 17h /
86 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7662d 08h /
85 Typo fixed. mohor 7662d 08h /
84 clk_cnt reduced from [8:0] to [6:0]. mohor 7663d 15h /
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7663d 16h /
82 Removed few signals. mohor 7663d 17h /
81 "chip select" signal cs_can_i is used only when not using WISHBONE
interface.
mohor 7663d 17h /
80 Form error was detected when stuff bit occured at the end of crc. mohor 7663d 17h /
79 Bit stuffing corrected when stuffing comes at the end of the crc. tadejm 7664d 17h /
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.
mohor 7664d 17h /
77 Synchronization is also needed when transmitting a message. mohor 7667d 16h /
76 Counters width changed. mohor 7667d 16h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.