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Rev Log message Author Age Path
48 linus 5538d 09h /
47 linus 5538d 09h /
46 linus 5538d 09h /
45 linus 5538d 09h /
44 more on directory structure markom 7633d 03h /
43 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7922d 10h /
42 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7922d 10h /
41 Changed synthesizeable FPGA memory implementation.
Fixed some issues with Xilinx BlockRAM
rherveille 7922d 10h /
40 Updated PDF. lampret 7966d 13h /
39 Added Richard's feedback. lampret 7968d 14h /
38 Undeleted mohor 7989d 03h /
37 no message bbeaver 8225d 09h /
36 minor changes: unified with all common rams samg 8245d 18h /
35 corrected output: output not valid if ce low samg 8245d 23h /
34 added valid checks to behvioral model samg 8245d 23h /
33 added checks and task in behavioral section samg 8247d 00h /
32 no message bbeaver 8248d 06h /
31 no message bbeaver 8252d 07h /
30 no message bbeaver 8253d 05h /
29 got timing checks mostly correct
No functional stuff yet
bbeaver 8253d 06h /

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