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Rev Log message Author Age Path
41 SIM:
- Update the wb_uart to a 8 bit system
- use ulogic		 ameziti 4603d 05h /
40 SIM:
- use external script for the Path		 ameziti 4604d 00h /
39 DEV:
- BUG : pop the stack also at "return I" instruction.		 ameziti 4604d 00h /
38 PRJ:
- remove automaticly generated code from svn.		 ameziti 4604d 00h /
37 SIM:
- validation of the wishbone timer interrupt access		 ameziti 4604d 00h /
36 SW:
- code for testing interruption with wishbone timer.		 ameziti 4604d 00h /
35 PRJ:
- remove inversionned files.		 ameziti 4604d 14h /
34 SIM:
- wisbone:
- add testbench for testing wishbone timer.		 ameziti 4604d 14h /
33 SIM:
- add path from script		 ameziti 4604d 14h /
32 SW:
- wishbone:
- add timer code software		 ameziti 4604d 14h /
31 SIM:
- wishbone :
- add some docs for "Wishbone Verification" methodology.		 ameziti 4605d 04h /
30 SW:
- wishbone :
- add asm code for the "wb_timer_08" wishbone validation test
- add asm code for the "wb_uart_08" wishbone validation test		 ameziti 4605d 04h /
29 SIM:
- wishbone :
- add constants value of the address of wg_gpio_08 internal registers		 ameziti 4605d 04h /
28 SW
- add asm code for the "wb_gpio_08" wishbone validation test		 ameziti 4605d 04h /
27 SW
- add asm code for the "wb_gpio_08" wishbone validation test		 ameziti 4605d 04h /
26 ameziti 4605d 05h /
25 SIM
- add ModelSim scripts for the "wb_gpio_08" wishbone validation test		 ameziti 4605d 05h /
24 SIM
- change the names format of ModelSim scripts		 ameziti 4605d 05h /
23 SIM:
- test the read wishbone instruction		 ameziti 4605d 06h /
22 DEV:
- wishbone :
- change the names of significants signals
- transport the data from the external component to phase2 write.		 ameziti 4607d 21h /

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