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Rev Log message Author Age Path
20 finished the stream_cypher module, this module passed modelsim , but doesn't pass veriwell, i don't know why simon111 5876d 06h /
19 add a modelsim project to samulate the stream_cypher module simon111 5876d 06h /
18 try to add decrypt module (not finished yet) simon111 5886d 07h /
17 finish block_decypher module simon111 5937d 13h /
16 add the block_perm and block_sbox simon111 5941d 05h /
15 finished key_schedule module simon111 5945d 07h /
14 *** empty log message *** simon111 5946d 07h /
13 add key_schedule module(note: this module is not right yet) simon111 5946d 07h /
12 *** empty log message *** simon111 5946d 07h /
11 add clean rule for some makefile simon111 5979d 08h /
10 add the sw simulate stuff for key_perm simon111 5979d 08h /
9 add the pli module and bench for key_perm module simon111 5979d 08h /
8 initial version simon111 5979d 08h /
7 fix the key_perm module simon111 5979d 09h /
6 This commit was manufactured by cvs2svn to create tag 'arelease'. 6288d 05h /
5 This commit was generated by cvs2svn to compensate for changes in r4, which
included commits to RCS files with non-trunk default branches.
Simon111 6288d 05h /
4 added a simple readme file and a testbench for key_computer module Simon111 6288d 05h /
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.
Simon111 6291d 02h /
2 no message Simon111 6291d 02h /
1 Standard project directories initialized by cvs2svn. 6291d 02h /

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