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Rev Log message Author Age Path
32 fix a compile error simon111 5705d 05h /
31 remove pc execute file simon111 5705d 06h /
30 begin vailating on fpga simon111 5705d 06h /
29 fix some bugs simon111 5706d 05h /
28 create a quartus10 project for test the core simon111 5706d 05h /
27 improve makefiles simon111 5706d 17h /
26 Added old uploaded documents to new repository. root 5742d 06h /
25 Added old uploaded documents to new repository. root 5742d 22h /
24 New directory structure. root 5742d 22h /
23 testing key_schedule module simon111 5826d 06h /
22 decrypt module testbench update simon111 5866d 05h /
21 decrypt module passed basicly, it's not good code type simon111 5866d 05h /
20 finished the stream_cypher module, this module passed modelsim , but doesn't pass veriwell, i don't know why simon111 5880d 04h /
19 add a modelsim project to samulate the stream_cypher module simon111 5880d 04h /
18 try to add decrypt module (not finished yet) simon111 5890d 06h /
17 finish block_decypher module simon111 5941d 12h /
16 add the block_perm and block_sbox simon111 5945d 04h /
15 finished key_schedule module simon111 5949d 05h /
14 *** empty log message *** simon111 5950d 06h /
13 add key_schedule module(note: this module is not right yet) simon111 5950d 06h /

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