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Rev Log message Author Age Path
35 csa cli support binary test data simon111 5701d 05h /
34 add binary test date (only sw_sim now ) simon111 5701d 08h /
33 improve ledseg controler module simon111 5701d 19h /
32 fix a compile error simon111 5701d 19h /
31 remove pc execute file simon111 5701d 20h /
30 begin vailating on fpga simon111 5701d 20h /
29 fix some bugs simon111 5702d 20h /
28 create a quartus10 project for test the core simon111 5702d 20h /
27 improve makefiles simon111 5703d 07h /
26 Added old uploaded documents to new repository. root 5738d 20h /
25 Added old uploaded documents to new repository. root 5739d 13h /
24 New directory structure. root 5739d 13h /
23 testing key_schedule module simon111 5822d 20h /
22 decrypt module testbench update simon111 5862d 19h /
21 decrypt module passed basicly, it's not good code type simon111 5862d 20h /
20 finished the stream_cypher module, this module passed modelsim , but doesn't pass veriwell, i don't know why simon111 5876d 18h /
19 add a modelsim project to samulate the stream_cypher module simon111 5876d 18h /
18 try to add decrypt module (not finished yet) simon111 5886d 20h /
17 finish block_decypher module simon111 5938d 02h /
16 add the block_perm and block_sbox simon111 5941d 18h /

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