URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 144

Rev	Log message	Author	Age	Path
144	Port names and defines for the supported CPUs changed.	igorm	7423d 09h	/
143	Signals for easier debugging removed.	igorm	7423d 10h	/
142	Typo fixed.	igorm	7423d 11h	/
141	data_cnt_lim length changed to reduce number of warnings.	igorm	7424d 06h	/
140	CRC checking of incoming CRC added to all tasks.	igorm	7424d 21h	/
139	New release of the debug interface (3rd. release).	igorm	7427d 00h	/
138	Temp version before changing dbg interface.	igorm	7433d 04h	/
137	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7437d 05h	/
136	Table describing chain codes added.	igorm	7437d 05h	/
135	'hz changed to 1'hz because Icarus complains.	igorm	7440d 04h	/
134	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7441d 03h	/
133	This commit was manufactured by cvs2svn to create tag 'highland_ver1'.		7441d 03h	/
132	Documentation updated. Many missing things added.	igorm	7441d 03h	/
131	Documentation updated. Many missing things added.	igorm	7441d 04h	/
130	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7483d 02h	/
129	New documentation.	mohor	7483d 02h	/
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7485d 10h	/
127	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7488d 10h	/
126	run_sim.scr renamed to run_sim for VATS.	mohor	7488d 10h	/
125	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7490d 06h	/