URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 19

Rev	Log message	Author	Age	Path
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8400d 02h	/
18	Reset signals are not combined any more.	mohor	8402d 11h	/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8426d 00h	/
16	bs_chain_o port added.	mohor	8428d 00h	/
15	bs_chain_o added.	mohor	8428d 01h	/
14	Document updated.	mohor	8428d 23h	/
13	Signal names changed to lowercase.	mohor	8429d 02h	/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8430d 02h	/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8450d 22h	/
10	First official release 1.0.	mohor	8455d 02h	/
9	Working version. Few bugs fixed, comments added.	mohor	8455d 02h	/
8	Asynchronous set/reset not used in trace any more.	mohor	8456d 00h	/
7	First official release 1.0.	mohor	8456d 00h	/
6	Minor changes for simulation.	mohor	8456d 00h	/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8456d 22h	/
4	Initial official release.	mohor	8461d 22h	/
3	This commit was manufactured by cvs2svn to create tag 'arelease'.		8461d 22h	/
2	Initial official release.	mohor	8461d 22h	/
1	Standard project directories initialized by cvs2svn.		8461d 22h	/