URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 25

Rev	Log message	Author	Age	Path
25	trst signal is synchronized to wb_clk_i.	mohor	8343d 23h	/
24	CRC changed so more thorough testing is done.	mohor	8345d 00h	/
23	Trace disabled by default.	mohor	8351d 02h	/
22	Register length fixed.	mohor	8351d 02h	/
21	CRC is returned when chain selection data is transmitted.	mohor	8351d 22h	/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8353d 01h	/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8365d 02h	/
18	Reset signals are not combined any more.	mohor	8367d 11h	/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8391d 00h	/
16	bs_chain_o port added.	mohor	8393d 00h	/
15	bs_chain_o added.	mohor	8393d 01h	/
14	Document updated.	mohor	8393d 23h	/
13	Signal names changed to lowercase.	mohor	8394d 02h	/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8395d 02h	/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8415d 22h	/
10	First official release 1.0.	mohor	8420d 02h	/
9	Working version. Few bugs fixed, comments added.	mohor	8420d 02h	/
8	Asynchronous set/reset not used in trace any more.	mohor	8421d 00h	/
7	First official release 1.0.	mohor	8421d 00h	/
6	Minor changes for simulation.	mohor	8421d 00h	/